Monolithic power integrated circuits (PICs) for high-voltage applications may sometimes integrate thereon a junction field effect transistor (JFET) and a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor. For instance, a JFET device may be incorporated in a power integrated circuit to use as a normally on pass device for a startup circuit. The JFET device may have a drain terminal connected to a power source terminal (e.g. 12V), a gate terminal that is grounded, and a source terminal connected to a power supply node for a load. As the power source ramps up, the JFET conducts current in a channel between the drain and the source terminal to provide power to certain circuitry of the load. When the power supply node (source terminal) to the load reaches the desired power supply voltage for the load (e.g. 5V), the JFET channel is pinched off and the JFET device is turned off. JFET devices are preferred in the normally on pass device application because of their good pinch off characteristic which ensures that circuitry downstream to the source terminal of the JFET is protected from the high voltage of the power source.
Meanwhile, LDMOS transistors are commonly used in high-voltage applications (20 to 500 volts) because of their high breakdown voltage characteristics and compatibility with CMOS technology for low voltage devices. In general, an LDMOS transistor includes a polysilicon gate, an N+ source region formed in a P-type body region, and an N+ drain region. The N+ drain region is separated from the channel formed in the body region under the polysilicon gate by an N drift region. It is well known that by increasing the length of the N drift region, the breakdown voltage of the LDMOS transistor can be accordingly increased.
When a JFET device and an LDMOS transistor are fabricated on the same integrated circuit, it is sometimes challenging to optimize the characteristics of both devices while maintaining a reasonably cost effective fabrication process. FIG. 1 is a cross-sectional view of a power integrated circuit including a JFET and an LDMOS transistor formed on the same semiconductor substrate in one example. When JFET 1 and LDMOS device 2 are manufactured using the same fabrication process, the devices have to be formed using the same diffusion regions available in the fabrication process. In particular, the traditional method for integrating a JFET into a LDMOS fabrication process uses the P-type body (P-body) region 4 of the LDMOS to form the gate region. However, the P-body implant is tailored for the threshold voltage in the channel and the breakdown voltage rating of the LDMOS transistor. The same P-body implant used as the gate region for the JFET device may not yield the desired pinch-off voltage to pinch off the transistor channel. For example, when the P-body implant is optimized for the LDMOS transistor threshold voltage and breakdown voltage, the JFET device may end up with a threshold voltage of 20V or more to pinch off the JFET conduction channel which is undesirable in the case where the JFET is coupled to supply circuitry operating at 5 volts. It is thus difficult to optimize both the JFET device and the LDMOS transistor in a power integrated circuit.